New Disruptive Microchip Technology and The Secret Plan of Intel

raising costs to make the economics work Intel needs to get creative here and it looks like they have some ideas on how to fix this and make it faster and cheaper. Their intention is to use direct self-assembly and to be honest this is a very complex process. I don't fully understand it because there's a lot of very complex chemistry involved. The idea is to cover the wafer with a special poly material and then bake it for about an hour and when it is baked, these materials self-organize into tiny lines and based on some research that was done earlier on this, we can use EUV machines to help guide the way it is arranged on the wafer, but the main problem is that this approach was in the research phase for about a decade and was not adapted because the defect rate was too high, but I really support Intel here because, For everything they did for the industry, I really want them to make it work, you know?

But now you're aware of all the different innovations that Intel is trying to implement at once over the next few years and how high the risks are, but if they make it work, especially node 14A, this will be the crucial moment in the Intel history and it surely will. help your stocks recover this video is already getting quite long but just a couple of words what comes next after the High NA EUV machines we will eventually get to the hyper NA EUV machines let me know if you want a video about this in the comments after the gate around the architecture, all factories will move to the next transistor architecture, the so-called complementary FET transistor CFET, and this will help us reduce the footprint even further and I really believe in the future vertical of transistors, the idea of ​​CFET. is to fold two nanosheet transistors on top of each other vertically to build a CFET structure.

Intel was the first company in 2020 to make CFET work by stacking an NMOS transistor on top of a PMOS. In this way, they build the simplest logic circuit you can imagine. CFET inverter when the input is applied to said circuit, its output is a logical inversion of the input, so if we have one at the input we get zero at the output and vice versa and it is a curious fact that even back then they had to use rear power delivery here and the reason is that when we stack devices the interconnect complexity on top just explodes so it's clear that vertical transistors along with rear power delivery are the future of transistors and the future of silicon chips.

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