Libero® Design Flow Using Libero SoC Design Suite v12.3

In today's training I will introduce the liberal

design

flow

presentation and also guide you through the liberal tools. Here's the agenda for today's training, so a liberal OC is basically the microchip. fpg is horrible software used to

design

f period. fpga designs from design input to programming and the deepest third point liberal polars is comprehensive because

using

the With a single tool, you can create your design from input to debugging programming. It is easy to learn because it is intuitive and is a GUI-based method. If you are not comfortable with that, think about those scripts, you can use the GUI visit to create your designs, it is easy to adopt because it is a single click from synthesis to programming and it supports all the guarantees that users need, so here's the cheers so basically we have two liberal editions one is the liberal IDE and the other is the liberal OC the liberal IDE is an old and legacy software used for the old anti fuse and RT families.

There are no improvements for the IDE, we actually fix bugs with service packs if bug fixes are required for the ID. The software on the other hand I guess liberal edition II has two subbranches one is level 0.9 and it is a respect so

using

this level nine and older versions of liberalized it is compatible with g3 families so g3 means preceptor igloo fusion and point fusion. families, it also supports g4 family, g4 makes smart fusion two and blue, two families and it supports RTG for family and for this branch there are no new improvements or features for this branch, we only fix bugs with packages of service. third, the second branch is the Cole point only. this point eight is compatible with affair g4 and RTG for families, so as mentioned in the previous slides, if you want to work on polis fire g4 and RTG, you can use them for 5x and then, because actually we have many features that also will be added in the next versions, if you are using older devices or older families then we need to use this version 1.9 or earlier versions, a couple of key features of the liberal X 12 point versions, so many features have been introduced .

With the center point It's very easy because all the inputs appear on the left side and the outputs appear on the right side. the canvas can actually highlight any network or instance, easily navigate your layout, it also supports hierarchical expansion in place, it will show it in the demo, so now we support technical base layout for smart layout, which means custom HDL IP and code configuration using the UI we can also support UN particular scripts. This is the design

flow

. The liberal design flow is complete. It has the complete toolset from design input to programming and debugging using design input.

You actually create or design using HDL stream or not. which is nothing more than this ematic input, once you create the design, you can do a functional simulation using similar simulation tools. We use mentor modelsim to integrate it into the book and then you create the generator synthesis. We use simplified pro until synthesis you can actually use. Liber tools can also use a third party to generate the netlist model until the synthesis stage, so we call it interface from place and route, you should use liberal software because it actually takes the resources available on the FPGA, so once you place your layout and connect the routing you do the timing analysis using the smart timing tool and you do the power analysis using smart power tools so once you are satisfied once the timing is met and a Once you agree with the power, dynamic and static power of your design, then you need to program the FPGA and use flash pro or flash practice tools, finally debug at fabric level at hardware level using smart debugging tool , which is the tool developed in-house by microchip and you can also use identify me from the synopsis to debug the FBI fabric and will explain each and every stage of this design flow design input.

It has two layout tree methods, one is HDL input and the second is this plant is an input that reaches HDL input. It has four components, one is the Hitch Custom HDL, so by using Custom HDL you can create your own design from scratch. We support the VHDL language. The HDL language system's role in registration and mixed language increases once you create your design if you want to create. an IP of the custom HDL, you can actually create the custom HDL IP, so in the same project, if you want to use the same HDL for multiple places in your module, you can create a custom IP to eliminate the hook and, using a layout smart, you can place these IPS and you will be able to connect all these IPS also schematically.

On the other hand, you have the rich teals of MATLAB using MATLAB. It is actually easy to create the BSB layouts once you create the DSP layout using the HDL Earth code, it will generate a generic HDL port. that HDL code we can actually import using this HDL entry the fourth is the dead course HDL so the direct cores are nothing but the internal microchip, the internal IP course for most of the IPS we provide the HDL source code which You can actually generate the HTML source code from the IP and we can use it, you can reuse it, you can modify it according to the requirements, but if you modify the HDL source code, the microchip will not provide any technical support if you create the HDL slope. a simple buffer VHDL code and if you want to create a custom ID from the HDL code in the book in the layout hierarchy, you can highlight in the HDL module, right click and there is an option to create code from HDL, so a once you click on this option it will create the custom IP so let's see the demo so I installed liberal 4.3 so once you click on it will open I will create a new layout if you want to create a new project you want to go to a new option.

In fact, I created a project name, it has a lab 1 and this is the location of the project. I would like to create the HDL code. Next is the device selection. I use Polar Fair and will choose MTF 300 Tears. I choose fcg for the package and the ball speed is excellent. So I chose the MPF 300 TS - 1 FC g 4 8 4 which I designed so that on this device selection page you can see all the resources that are available for this particular device, such as what are the flip-flops available, what is the user. was available and so on.

If you know the part number, you can provide the full part number here. The tool will then automatically highlight that part number for you and the device configuration page for the polar show. We currently have one world and one world 1.05 selecting. a world and this is the default value that I was accessing, so here I have the couple that I was trying to say. I can choose any of these. It was standard. If I sell it, they will see me at most. One finds eight words for the entire user. I'll go with this lvcmos 1.8 above, but if you want to change any of these, you can change them using the I/O editor.

In fact, I'll show you the grease tool in the next lab, so here's something. called preserved pins for probes Philosopher's has two dedicated pins that are used for debugging the FPGA design, so you can call any internal signals to these external pins and monitor the behavior of these signals using the scope, so if you don't want to use them you can uncheck this option when you uncheck this option then those two pins can be used as general purpose. I go, so I have both entrances and the door open and I have no time constraints, I just keep that tab.

I have a layout hierarchy. the complete layout for which I explained in the presentation under layout flow is available here for you and in the layout hierarchy, whatever HDL port we just imported will appear here, so once you create a hierarchy, in will actually build the design and if you write the HDL stimulus files will be available in this tab and we have many pipelines, the course depends on the signals, you can actually select any of the era such as IP DSP cores and active cores macro libraries of processor, it has many bus interfaces, it has many IP cores available here, so all these other IP codes are developed using microchip.

It is an internal IP course. Now it actually asks me to set the path to right click on the HDL module and set this module as root, so I actually show you the name of the root module here, which is an HDL underscore. I would like to create a smart design. I mean, I would like to create an IP core from HDL. I can right click and I can select create or from HDL. So so far, it's actually showing up as a VH VHD file, so when I click Create Core, it's going to be like the HDL plus file.

When you create a core, you can also provide burst interfaces to IPs. I am currently not providing any personal interface. the HDL HD client as it was created so I'm going to show you how we can call that custom HDL into smart layout because my layout actually supports this custom made steel in the smart layout canvas so using smart layout it has multiple IPS yes If you want to create an embedded design you can create a shadow design using the 32 bit risc five IP which is available as part of the liberal IP catalog and with this IP catalog you can use any of these IPs and create your own design. using smart layout canvas, which will really save your time because if you want to use f15 or layout, you have the main SSP available in the catalog, we can drag and drop it directly and you can also configure the IP parameters according to your requirements.

Support add-on code which means third party IP course but it is not available by default if customer pay for IP so partners will provide CPC files which is like IP file which in Libram can import that third party. Party IP at the highest peak at work, so I already explained about this custom HD, like when I show the demo, actually I will call it custom IP and also call the core IP catalog and create a smart layout for many of these points are covered in the previous slides. The important point I would like to make here is the expansion of intelligent design within intelligent design, so you basically have a place brand here, so this is a superior intelligent design, one of the best.

Madison block, if you open this, click on this placemark inside which you have sub-smart design components. You can completely see the hierarchical view of all the components of my child layout once you click on this placemark, so I didn't do the demo, so now. I am creating the smart layout block. Create intelligent design. In fact, I'm going to go to this design hierarchy now in this lab. This is a cleverly designed canvas. On this smart design canvas, I'm actually going to place these two entrances and doors, and I'm going to go as well. Go to the IT catalog and select and press the macro.

Now I will promote them. I go to the top level module, so when I promote the top level modules, like I said, on the left side you have the inputs and on the right side you have the outputs. I can also modify the name of the input or output port. Now I generate this mod layout. I need to generate the component once I generate the component and build the hierarchy. This lab for the smart design block under that smart design block by steel place is available in the lab for the component, so if I create another one, for example, I want to create an entrance and a door using the three, two entrances and a door, then I will do it.

Actually, I'm going to you and I'm going to a design and I'm actually going to call the lab tube. Look this. I have this is the top component below which I have two subcomponents and I can actually call the other one. I mean, I can actually create an instance of the Same there are two entrances and doors and they are connected so that the Y exits a a when the score is 0 and I can promote all of these Bibles to the top module, so that once created, the v2 Have the Lab: Smart Design Block Below Top Module v2.

So if I create another smart layout block, why do I want aonly intelligent design component for the four entrances and the door? So this is just an example, so I just want to show how we can expand and what the intelligent design hierarchy will be like. I found it, now this is like a door and four entrances, if you expand what you have, we have a lab for a smart layout component and if you expand it, this is the hierarchical view of the top smart layout component, so in that lab Basically, I covered how to use this HDL module, which means the custom HDL in multiple places in the same layout and also talked about how you can create a top level smart layout component.

Now let's see the flow of improved constraints basically if this is so. the typical liberal design flow especially, then we complete the design in free flow and now we are in the implementation part, so for the implementation you have the synthesis listener out and pending verification for the implementation you have to provide the constraints for the implementation block, so for Synthesis, you can provide the timing constraints, which are the derived constraints, which are like the user, which is like an SDC file, and you can also create FDC constraints, which are FPGA design constraints From the synopsis, there may be multiple attributes available in the FDC. constraints document, so you can create the FTC file and deliver it to the synthesis place, so before placing and annotating the design, you actually need to give the design constraints, which again are time constraints, which is the file dot SDC and also It is necessary to give AIBO constraints, flow plan constraints and NDC constraints which is a list of nets.layout constraints so NDC is used in the compile stage basically if you want to do this , I would combine Pascua, you can actually create that in the NDC or if you want to preserve any of the signals if you think that any of the signals are missing when you are compiling the layout, you can preserve those signals using the NDC files.

PTC is nothing but flow plan constraints, so you can lock the layout location using these PVC constraints. I have a constraint, as you know, it is a SP Giro constraint that will provide. the FB pin names for your layouts at the time of verification it actually provides to negate the restrictions which is an SDC dot file basically in our policy our FPGA for the integrated blocks like the surlis transceivers or for the ccc block or for the MSS block. If the tool actually creates the constraints for you, so we already developed the constraints created for you, there is only one option to choose and there are constraints, click on it will automatically have constraints like dc5 feet, most of the points are covered in In the previous slides the main thing is that the enhanced constraint flow is a centralized tool that is used to apply all types of constraints in a single user interface that I mentioned in the previous slide, you can apply the revealing constraints EC main scheduler constraint and type of EC constraints that you can apply in a single tool and you can also check the syntax by using this tool even before going to the implementation part, which really saves your time, so instead of covering the constraints manager in the presentation and then guide you through the Lib routine. and show how constraints are placed to apply constraints, you need to go to the constraints management UI.

It has its attribute used to provide IO constraints. It has a time tab which is used to provide the time restrictions. You have the floor planner tab which is used to provide the floor plan placement and routing constraints and finally you have the netlist attribute so this is the next attribute tool. You can create NDC or MPC files using this and a test attribute, so in the Voy attributes you can provide the I/O. constraints either through a text file using the text file or you can also create the I/O constraints using the editor I was editor so if you see the I/O text file, that is the file PDC, you can configure the Ibis, this is the Ivo set what is the port name, so this port name is nothing but this is used in your design under the entity and for this port you are assigning the SPG in the name of the pin and the pin name is h7, this is a fixed pin and what is an input address for each "who" will provide restrictions like this.

If you know the syntax you can write and update these PDC files or if you don't know the syntax you can go to the editor which is UI mode. and using this IO editor you can apply the diver constraint, then this is the aegyo editor tool. On the left side you have the port view, you have the logical location view and you have the networks that are loose to create your connection layout, you have the following view and you have the regions view on the right side, you have the port view , so this port view is used to show everything that you have used in your design in the entity section or whatever port names you have. it will show up here and baseball and you can actually select that as input or output based on your HTML layout, it will actually choose input and output automatically and like I said, initially it was standard, we also set CMOS 8 to 1.8 volts.

So I'm going to show that by default for sir disclaimer the group will select the I/O standard so you don't need to select anything here and these are the FPGA pills so it actually sells if the FPGA pins They are based on your personalized license plate. once you select the FPGA pins, it will be locked based on the pin number, it will select the bank name automatically in the pin view, you will be able to see all the pin names, the SPG IP numbers available to you will be FPGA selected and, if you see the lock option here the lock column here if you already assigned the layouts it will actually show you that these were already assigned to me see this you already have a lock symbol here so on the outside you have the reference clock, this is the reference clock and you have the TX PLL component this is the TX PL component and you have the quad lane assessment currently I am using chord 1 quad 1 each quad forelimb currently for my layout I am using lane 1 q1 so if you see this view at the top modules, I mean the top quad, I mean the quad 2, which is in gray color because this reference clock cannot be used at this stage because the reference that came from here cannot be connected al q1 squared, so that's why it's the gray similarly, you can't use the bottom quad for the other locations, you can actually change the locations from here to here and any other places you have.

Similarly, you have a memory view here and you have a package view where it will actually show you the unconnected pins. the unassigned pins the fixed pickups how you like the ground and the VCC pins this is the third plan view. I will talk about this program and then I open the arc planner in this attributes tab aegyo if you create the constraints if you create the OPD C file In fact, you can use the same constraints that I will do and you can select any of the devices available in this section to be able migrate your device to a higher device if, for example, you are currently working on 100 T. device and if you see if you think that the logical elements that are available in 100 K hundred K are not enough for you, so you can import the same design to a 200G device, you don't need to change the restrictions here. that's the best advantage in the sync tab, as I mentioned it uses the SDC files.

The SDC file format is used for time constraints. If you select these derived constraints, the tool will automatically create constraints for the embedded blocks that are available in the xpg. like I said, like surveys or PCI Express or MSS, the new option is used to create a new SEC file, so all these options are basically, I will be in almost all the tabs, so the entry, if you already have the DC file available and If you want to import that same SDC file in this project, you can import it now if you don't want to import the SDC file but just want to link the SDC file which is available in the other location which you don't need. to copy that SDC file to current project, but you can just link it, you know the syntax, you can write the constraints using SDC files, you can use SDC file in synthesis stage or in placement path stage or in verification stage of time.

I have clock constraints that are like a hundred megabytes and I applied to the user constraints SDC file and now in the second SDC file I applied 200 my marriage as clock constraint, so if we apply the same constraint and with the different values ​​in the multiple SDC Files, the tool will select the latest SDC file that is available in this UI, so be careful while applying time constraints as in seaplane constraints mainly location constraints are used, so all these I already explained the options in the previous tab. I can actually see the placement constraints using the chip planner and you can actually modify it.

You can block locations. You can create regions and lock the region as per my design. My logic is placed in this area now if you expand the location. You can see up to the door level players can drag the location to see the location using networks. I can actually see the connectivity of my layouts, so here's the location, here's the wolf, so I can see the routing part from the I'm going to the logic and the I's logic is that if you want to create, if you want to create regions, one in the regions lock you can expand these macros and in the floor plan view you have to create an empty region, create an inclusive region and create exclusive regions using create. empty region we are guiding book software to not use this particular region to place logic because it will use that area for any other blue logic in future so it is saving that region for future use and if you use create inclusive What happens is that if the logic is placed in a particular location and you create inclusive for that particular area then you are basically guiding the tool, don't disturb the logic available in this particular region, you can use this region for routing resources and when actually creates exclusive, then you are guiding the tool to not use this exclusive region for routing sources.

I can also create any of the regions in any of the places, so here I have something called region step and then the regions are created. you can rename this region, on the other hand it has one attribute at least. Actually you can create the NDC file or the FEC file, so the compiled netlist constraints are the NDC file and simplified from the synopsis, the simplified netlist constraints are the MPC file, so there is no editor. or there is no tool to create the constraints, if you see this NDC file, it is actually guiding the tool to preserve this instance, so I covered the demo to improve the flow of constraints.

We use synopsis tools for synthesis. I already explained it in the previous section. flights using synthesis, it actually creates a gate-level optimized netlist, if you want to create our state machine, you can also create a state machine using the simplified rules, this simplified will support the itv1 735 encryption standard, so If it has it, it encrypts its HDL code. Using this standard, typically 1 P 1 7 3 5 e, synthesis will allow you to synthesize what's coming to the timing analysis, so you've basically already created the constraints using the constraint manager. Your time width can do the full time analysis of your layout and it will really ensure that you meet all the timing constraints, see the timing constraints UI, you can see the log to record routes and here in the part bottom, it can tell you how the slag distribution is in your design if the slack is positive then the timings are met and each path, each source pin and the sink pin, it will actually show you the delay and the slack value and each time it will require a time setting value and it will also show you those Q values ​​if you double click on any of this path it will actually open the UI smart time where it actually shows complete from clock to data and to that clock up to the data, it will actually show all the components if you see here if it's from the clock source. to the destination data, so from the clock the data will show all the components and it will show the delay of each component and if you calculate the arrival time for the route and for the same route and the background, currently I did not show it. the calculation of the time required for the data at the bottom has the time required for the debt data, so the time required for the data: the arrival time of the datais a slack that should be positive and then the other important feature of smart timing is that you can actually test the signals or the instance of the smart tools to the chip scheduler, which is the flow of the scheduling tool, so when use power analysis, it will actually analyze the static RAM, the dynamic power of your design, so power analysis is very good in terms of visualization, so you can actually calculate each and every component of its design, so in the FPGA we calculate what is the dynamic power of the I boost and what is the dynamic power of its logic.

What is the dynamic power of their names? What is the static power? was consumed during the course for memory, so each and every component will be shown to you and there are multiple scenarios that you can apply, such as operating conditions, which you can change and see how the results change so that you really we can apply. multiple scenarios and play with the programming of this smart power tool, so that once the time is up, once you are satisfied with the static and dynamic power of your design, finally program the FPGA using flash Pro or there are multiple methods to program the FPGA check if you see the programming methods, you can program the FPGA using a Pro flash, you can also program the xpg using an external processor and finally you can program the FPGA using the FPGA itself because inside there is something called system controller The system controller acts as a spy master and will program the FPGA so by using the flash probe and external processor both modes support JPEG and Spike programming and as I said inside the FPGA you have a system controller which acts as master spy.

Basically you are actually programming the SPK using the external spy memory using this spy master so you have two modes one is Cata mode so Auto means the FPGA is automatically programming the FPGA using the spy master and the AP ID application. Basically, it does the different types of services for you. If you want to read the index of external spy flash, you can use this file interface. You can actually read the base address of bitstreams, so you can use AAP applications. and in automatic you have two different modes, one is automatic programming, which means that if you have a blank FPGA and you are programming for the first time, basically from the factory you get a blank FPGA, now you are programming the first thing from the external. spy bar and if the external spy bar has three different bitstreams version 1, version 2 and version 3, it will actually program the latest version that is available on the external, the highest version, which means version 3 file bits which is called auto programming if you are programming for the first time and on the blank device it is called auto programming now the second one is auto update.

The update will compare the large file version available on the FPGA with the bit file versions available on the external spy flash, for example I have in - PJ a bit file version - now all the extra slash notes I have mixed together in cellsversion 1, 2 and 3, then what happens is that upon power reset, the spj will be programmed with the version 3 bit file, front and external expiain flash which is called auto update, auto recovery, so when it is programming the FPGA and While programming the spca, if an interruption occurred and I went to an unknown speed, then at that time this recovery will try to reduce the fpga, I mean the xpg programmed with the highest portion of the bit file that is available in XML. flash, so on the debugging side, we have the best differentiated debugging tool in the industry.

It doesn't really need any FPGA resources for people, it's a framework to debug the memory available in the framework to debug the transceivers, it basically doesn't need any resources. people from the FBI fabric team and you can actually change, I mean, you can change the probe points on the fly without recompiling the entire design, without recompiling the design itself, so you're basically saving time because you're not By recompiling the layout and you're saving the resources for your layout because you don't need the xpj resources to debug your layout. Those are the two basic advantages to merge the intelligent more deeply in this training.

I explained design input, the whole liberal design flow from design input to programming.