Developing with PolarFire® SoCMar 17, 2022
hi everyone my name is hugh breslin and i am a design engineer working for a microchip today i am going to talk about the development of polar fire slc so we are going to cover and i hope by the end of this session it will have lived up to the tagline less complicated than it sounds but in depth what we're going to try to cover is application functionality and monitor kernels in
polarfiresoc and we'll see how to develop for bare metal and I'll also briefly touch on linux and then we'll see how to develop for an fpga so hopefully by the end of this presentation you'll have an idea of â€‹â€‹how to develop a polar fire slc and it won't seem as complicated as it might initially seem to start with a new architecture so to start off just briefly let's take a look at what
polarfireis, making it the world's first risc-v. based on soc fpga so we've had polar fire um fpga has been around for a while now it's a very good family it's d going pretty well and if you look at the picture on the right hand side now and you can see I have the fpga and the slc so when we talk about polar fire and that's our fpga fabric and if you bought a polar fire fpga you just get a full blue block and with all the programmable logic built in but with polar fire slc we add the soc part in the top right by removing part of the fpga fabric and put it into our microcontroller subsystem that contains our application, monitor cores, and some peripherals, and which can then interact with the fpga fabric, so there's sort of an ongoing myth that a running line that fpgas is quite complicated and with what we've produced with polar fire slc it's actually, it's not that complicated to start trying to do your development, whether it's hardware development for the fpga framework on yeah or software development and bare metal or linux for the soc mss part and really what we've ended up with is a produ ct that's pretty dynamic because you have the power of the fpga and its framework and you use the power of the soc and when you put those together two you get a really awesome system well this is like we said world's first risk 5 based soc fpga but what we've noticed in the grand scheme of things is that the risk 5 side has been invisible because it just works under the hood and when it comes to building your software you're going to build it with a different compiler to target risk 5 but you're still going to be writing C code or if you're writing a linux app that's going to be written relatively the same um so the risk five as a transition is really not that hard to do and very hard to notice. the difference when you're leveraging polar fire slc um and what i hope by the end of this presentation is that you'll see that we can't be completely invisible and so we have to implement like microchip but we can be transparent and i think we've really done a very good job to stay transparent in everything we've done allowing users a lot of flexibility and understanding to do what they need to do so let's take a look at the product in a little more detail and start with our mss so we have five cores in the microcontroller subsystem one of them is a monitor core so it's a sci-fi e51 and as you go there's nothing architecturally to say it can't do anything it's just not as powerful as the ones other application kernels only four application kernels which are sci-fi view 54s so application kernels that boot and run linux or your applications s bare metal or orthos and other working kernels and the monitor kernel can watch over the system it can boot and reboot a core that might have crashed and can provide some system services in between cores so we'll look at those a bit more in detail in a minute and then in addition to the course we have built in peripherals and I just listed a few here so we have usb uart with can with gpio ethernet ddr with mmc there are tons of things actually built into the mss that are available as peripherals for all cores so that's something that's really useful and so do you have your fpga so the fleece fire fpga with it's programmable logic uh you've got surges you've got pci and you've got math blocks you can take advantage of you've got sram available through the fabric so there's really quite a lot um and like i said when you combine the two the mss and the fpga you end up with a lot of freedom to develop what which you want and you end up with a lot of flexibility and because you can instantiate additional components in the fpga framework and use them from within the mss or if you were primarily using the fpga framework you can offload some work into the mss so you can do a lot of what you want to do So let's look at the course in a little more detail and I'll start with app c Of course the u54 cores are 54 cores and what's quite cool is that you don't have to use them all at once you can use several different configurations you can think of, so let's say you just want to run an app on Polar Fire. soc, you can target a single application core, you could target two of them, three or all four if you wanted, but another use case might be someone wants to target a single application on one core and three other cores, so a oneplus 3 situation where the single app could be a crypto app running and then linux is running on the other three cores so we can support one plus three you could do two plus two two kernels and a kernel and a kernel or four individual applications running through four different cores so that's quite interesting you can do a lot with it but how do you actually configure the system so that an application runs on one core and not in another heart and how do you do it? having another application that runs independently, say three of the hearts, is actually not that difficult and this is where, being transparent, we relate to it, so throughout our how we have several very useful definitions to use which are actually insanely powerful so we have these two here that I've shown what is the first heart of mpfs hal and the last heart of mpfs hal and you can see that the first heart is set to zero and the last heart is set to four , well the value of the last core is zero and basically we have a list of cores where the e51 is the zero core which is the monitor core and each of the u54 starting at one up to four are listed so e51 is hot zero u54 underline one as heart one q54 underline two is heart two and so so with these definitions set the way I have them to zero and four this application will use all hearts but lets say which we changed the value of the first heart to be two that means now the e51 and u54 underscore one ar It will no longer be touched by this app if they tried to run the app code let's say when they reset the reset factor of this program, they just went into an interrupt wait loop and wouldn't actually do it. run any code so that those two cores are killed with the first core value of two and then we have an app that will run on three of our u54 cores and we wanted to limit an app to only run on a specific core let's say the first application core e54 underscore one, we just set our first core defined to one and our last core defined to one and we've configured the system so that we have an application that will only run on an application core and if you set the first core to a value of two and the last actual value of four, you have an application that will run on three of the cores, so you'll change two lines and software settings that actually completely reconfigure how applications will run on the system, but you may also want to target a specific core, so you have application code that will run on three cores .
How do you ensure that the code you are using always works? to run on a specific core, but this again isn't too hard to do because what we've done is set up our projects so that if you provide a function with the name of the core, pointing to the first core of the application in this case, that it's the underscore u54 if you provide this function and when the heart of the heart starts it will jump to this and start executing code from it so this is our main underscore u54 function now what's quite useful is that if you don't To provide the function for this, you don't necessarily have to disable the heart.
We have provided a weekly linked function for each of the cores in the system, so if we leave our first and last startup defined, our app can use all cores but we don't provide a function for u5 4 underscore four, it will just terminate on its weekly hook function and we'll weight it to break mode so it's pretty clear what's going on you can walk through our startup code and easily see all this happen but changing some defines that are very easy to see and they are all listed in certain files you can reconfigure the way your system boots and if you want to target specific app hearts and run some code that is also pretty easy to do just using the features we provide and in terms of your development , if you would like to do some bare metal development we have the soft console ide available for that and if you would like to do al go linux development then write your own applications or if you were putting some custom logic in the fpga fabric and wanted to write a driver for it, we provide the buildred SDK and yoctobuild system via github so you have access to them when it's all about writing software to run in our application course I just want to talk briefly about the monitor kernel, what is the e51 and what is its purpose and what is it doing while your linux application and su and orthos are running together or whatever configuration you have for the e51 to run the hss which stands for heart software services so the hss gives you some system services and allows you to share messages which is quite useful and in this setup here on the right hand side we have a communication there between our u54 application course which is provided by a tool called the secure software messaging bus or ssnb and that allows you to Lets send a message let's say from u54 underscore one q54 underscore four then a message from linux to orthos and through the hss or let's say linux let's say our orthos is running some kind of cryptography program for us or some image processing or getting data for us linux can use the ssmb to send a message to the orthos to tell it to do a function or vice versa so that's pretty handy and then the hss also gives us our boot so it acts as a zero stage bootloader if we have an application stored in a non-volatile memory like sd card or in emmc, you can boot the system and load the application for us and store ddr and then start the course of the application so that it provides many or quite a lot of very useful services for our system general when we are running and just before we start and then let's take a look at some developments so we can have done a na overview of all our hearts and what we have provided that allows you to get started very quickly with your development well for bare metal huh we have created the polarfire library soc bare metal is a repository on github and there I have a wide range of examples as well which on the right hand side i took a screenshot of the most recent examples folder and we have an example basically for each of our controllers so all of these work in our smooth console ide and like i said that's where you go for your bare such development and each example project um we bba will be based on a peripheral driver and some drivers have multiple projects for example mmc driver gives you multi block projects or multi block transfer projects multi block transfer projects a single block and the main purpose is to Demonstrate each of the functions we provide in the driver, so for uart we provide an initialize function and a stream function for you to get examples of how to use them, and if you want you can just copy and paste our examples into yours. project and you can use the peripherals that way so it's a really quick way to get started and it's a great resource to be able to use and the soft and soft console can build those projects for you you can debug them by running them on a hardware target or you can emulate them too and because the software console has a three micro node emulation platform built in we have a polar fire soc platform in renode along with the icicle kit board support which is our polar fire soc and the starting platform so in the software console you can test all these drivers and you can test them without even having hardware in front of you so it's very very useful and the bottom line is that allthese examples are preconfigured for you, so they are preconfigured for the polarifier slc system, but they are also preconfigured as software projects, so all five risky extensions are targeted at you, the linker scripts are configured, any configuration The build file for the project is pre-configured for you as a starting point instead of having to start from a blank canvas and create a new project from absolutely nothing, you can import one of the sample projects and the mmu art interrupt project is kind of our go to show that in a second and you can import those projects and start
developinginside of them and which saves you having to go through all the steps to start from scratch so this is a useful resource to learn how a controller works, but it's also very helpful to get started quickly and just to take a look at what you actually provide in terms of our sample code, so I took a snippet of some of the sample code that we provided in our nmuart intro project, so if we just take a quick look at that at the top, we initialize our mutex so you can see how I have set mutex for our interrupts in polarifier soc then we initialize the uart itself so we initialize mssu to zero and set baud rate, data bits, spoof, stop bits so you can copy and paste literally this in its um its our own software project then we set up our rx interrupt handler so if we get a message sent to the system we'll get an interrupt and enable that interrupt so again very useful and if you want to use um install it yourself and then we demonstrate how to do a poll transmission from this uart and then we're also using we also demonstrate So that's how to use the mutex and we demonstrated an interrupt controlled transmission method so depending on your different application what you want to do and we've tried to show you all of the different ways you can use this peripheral so when we've done for uh uart it's pretty easy to show but we've done it for all of our different peripherals that are present in the system and if you briefly touch on linux and what we provide there like i said we provide and the builder sdk and we also provide the platform yakto and in that, what's quite useful is, um, it has our full commit history and development history for those platforms, so if you've developed your own linux application that you want to add in um or in the build system or If you developed your own driver for a custom peripheral that you built on the fpga fabric, you have our full commit history for when added to yakuto and buildroot as we go along so I had a quick look around and was able to find the confirmation of when we added our pcie driver so you can see all the changes that were made to add that driver and if you're trying to do the same yourself and c a foundation of what you do from work we've done ourselves before and finally let's take a quick look at the fpga development side so in terms of fpga development we have version 12.5 and above of the slc book design suite eh with support for polarfire soc so you can use book to generate reference designs and also add and remove from fpga build so you can build on top of our design out of the box using our icicle kit reference design repository so we have provided it on github you can download the repository and run a script in the book that will generate a reference layout for you and these are the d reference designers who were there when you were recording this and you run the script and you have the full design you would find in your icicle kit right in front of you so if you want to add your own peripheral to the fabric you can add to the design you already it's there instead of having to recreate it and try to figure out all the different aspects of the fpga you can target what you'd like to develop specifically so that's been a quick look at our fpga development so just to recap so what is polar fire soc? and so it's world's first risk 5 and based on risk 5 soc fpga and the main point is that it's actually very easy to develop as we give you everything you need to get started along with lots of examples and it's highly configurable so depending on what application you have in mind you can first configure it's pretty easy to do what you needed to do and finally I initially said risk five in polar fire soc is actually pretty invisible it doesn't have much of an impact in the development of your development and you don't notice it when you are actually running code um but we said ourselves that we are transparent so how are we transparent and what do we do right?
We use um smart definitions or very smart finds throughout our code so you can quickly reconfigure polarfireslc as a system and changing a line or two of code and defining or undefining some variables and then we also give you quite a bit of information so we have our build systems like yocto and builders with full esports and platform support for polar fire soc and the icicle kit along with our commit history so you can see the work we've done and how we've done it which is very helpful for maybe build on top of it and then we have all our peripheral controllers available for bare metal along with examples of how to use all the different features of the controllers and the last thing which is quite helpful is that we provide clip art for people who don't want to build a certain aspect of the system, so in total for polarifier slc to boot linux for example you need a fpga programming file you need the hss to boot the system and then you need a payload which would be your linux image we provide people with a fpga bitstream which also contains the service core software ices as a client so you can program that into your board without having to configure anything and your fpga part is programmed in a known good state and you have the core software services programmed into your envm for you so if If you were building custom linux images all you need to do is program your custom build and if you just want to build or build for fpga and make sure none of your changes have broken linux boot then we provide you with pre-built linux payloads so you can simply program them together with our tickle scripts to generate a reference design that matches what we have produced. or and programmed into the boards at the factory so hopefully that helped clear things up a bit.
I hope it shows that polar fire slc is very easy. to really get started and build and how transparent microchip has been in what's provided and the different tools we've used so thank you all so much.
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